1. Field of Invention
The present invention relates to a comparator. More particularly, the present invention relates to a comparator capable of receiving different analogue input signals and rapidly producing an output signal that distinguishes between high and low potential.
2. Description of Related Art
For the various types of analogue/digital (A/D) converters (for example, flash ADC, Interpolation ADC, Pipeline ADC and Two-step ADC), high-speed comparator is an essential internal component.
FIG. 1 is the circuit diagram of a conventional comparator. As shown in FIG. 1, the devices including PMOS latchp114, PMOS latchp212, NMOS latchn120 and NMOS latchn228 together form the regeneration stage of a comparator 28. The devices including PMOS resetp116 and PMOS resetp210 together form the reset circuit of the comparator 28. The devices including NMOS minm 22 and NMOS minp 24 together form a group of analogue amplifying circuit in the comparator 28. The device NMOS strb 26 serves as a current switch for the comparator 28.
In FIG. 1, when a latch signal with a low potential is applied to the input latch terminal of the comparator 28, the device NMOS strb 26 is in an open-circuit state while the devices NMOS resetp116 and PMOS resetp210 are in a conductive state. Hence, the output terminal outp and the output terminal outn are reset to a voltage vdda. When a latch signal with a high potential is applied to the input latch terminal of the comparator 28, the device NMOS strb 26 is in a conductive state while the devices NMOS resetp116 and PMOS resetp210 are in an open-circuit state. The group of devices including PMOS latchp114, PMOS latchp212, NMOS latchn120 and NMOS latchn218 are triggered to initiate regeneration. The input analogue signal sent to the input terminal inm of the device NMOS minp 24 is compared with the input analogue signal sent to the input terminal inp of the device NMOS minm 22 until the terminal, among the output terminal outp and the output terminal outm, with a higher potential are found.
FIG. 2 is a graph showing the results of simulating the operation of a conventional comparator. As shown in FIG. 2, the voltages at the output terminal outp and the output terminal outm must drop from vdda to about 1/2 vdda before PMOS latchp114, PMOS latchp212, NMOS latchn120 and NMOS latchn218 of the regeneration circuit are within the active region and able to find out which of the terminal among the output terminals outp and outm has a higher potential.
Since the voltages at the output terminals outp and outm must drop from vdda (the 3n axis position in FIG. 2) to about 1/2 vdda (the 3.2n axis position in FIG. 2) before PMOS latchp114, PMOS latchp212, NMOS latchn120 and NMOS latchn218 of the regeneration circuit are within the active region (transistors together have a positive gain), operating speed of the comparator is ultimately limited by the dropping period.